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Majority Logic Circuit

IP.com Disclosure Number: IPCOM000093065D
Original Publication Date: 1967-Apr-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Gardner, PA: AUTHOR [+2]

Abstract

The circuit performs majority logic. The voltage at output terminal D indicates whether a majority of positive signals or a majority of negative signals is applied to the input terminals A, B, and C.

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Majority Logic Circuit

The circuit performs majority logic. The voltage at output terminal D indicates whether a majority of positive signals or a majority of negative signals is applied to the input terminals A, B, and C.

The circuit consists of an odd number of differential amplifiers connected between conductors 1 and 2. Each amplifier consists of transistors T1 and T2 connected as a long-tail pair and having their collectors connected to conductors 1 and 2 respectively. The latter are connected through load resistors 3 and 4 to a supply voltage. The base electrodes of the T2's are maintained at ground and input signals are applied to terminals A, B, and C. A positive input signal applied to a differential amplifier causes T1 to conduct and T2 to be cut off. A negative signal causes T2 to conduct and T1 to be cut off. The voltage levels are chosen so that no transistor saturates. Since there is an odd number of differential amplifiers, a differential voltage is produced between conductors 1 and 2. The magnitude of the voltage difference between conductors 1 and 2 depends on how many differential amplifiers are in one state with T1 conducting and how many are in the other state with T2 conducting. This, in turn, depends on the polarity of the signals applied to A, B, and C.

Conductors 1 and 2 are connected as inputs to a further differential amplifier consisting of transistors T3 and T4 also connected as a longtail pair. The differential voltage on the two cond...