Browse Prior Art Database

Demand Response Interface Extender

IP.com Disclosure Number: IPCOM000093079D
Original Publication Date: 1967-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Greaves, JR: AUTHOR [+4]

Abstract

Decreased speed resulting from long distance data transmission between demand response interfaces is overcome. This is effected by interpreting the interface at an adapter which serializes the interface information for transmission over extended distances to another adapter. The second adapter reconstructs the interface appearance thus providing an extension between channels and control units that is invisible to either end.

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Demand Response Interface Extender

Decreased speed resulting from long distance data transmission between demand response interfaces is overcome. This is effected by interpreting the interface at an adapter which serializes the interface information for transmission over extended distances to another adapter. The second adapter reconstructs the interface appearance thus providing an extension between channels and control units that is invisible to either end.

Heavy lines in the drawings indicate multiconductor connections for byte transfers between components. Channel 10 provides a demand-response interface normally interpreted directly by a control unit or units 12. This interface includes a plurality of both input and output tag lines 13, output bus 14, and input bus 15. Adapter 18 interprets the demand-response interface signals, serializes them for transmission over duplex serial circuits 17 and 19 to remote adapter 20. The latter reconstructs the interface of 13...15 at 21...23. Both 18 and 20 function in such a manner that they are invisible to both 10 and 12 which are apparently directly communicating with one another.

In a typical initial selection sequence across a demand-response interface, tag line 13 is raised to indicate that an address is placed on 14. The addresses of all control units 12 to which the 18 and 20 adapter combinations are connected are stored in comparator 25. If the address on 14 compares favorably, it is gated into address register 26. Selection controls 24 cause control character generator 28 to place a control character into write shift register 29. The control character is then serially transmitted to adapter 20 by shift signals from write controls 38 to alert 20 that a demand-response interchange is about to occur. Controls 24 raise a tag line 13 to 10 and gates the address in 26 through 31 to provide a response to 10 through input bus 15. This indicates that a connection is completed, since a comparison at 25 presupposes an ultimate response from 20. In addition, the content of 26 is gated through gates 33 and 34 into 29 for serialization to 20. Synchronization by idle character transmission and reception between 18 and 20 by circuitry, not shown, maintains an indication that all control units 12, connected to 20, are operational as are 18 and 20.

Channel 10 next raises another line 13 and places a command on 14 which 24 gates into command register 35. Decoder 36 recognizes the command and, for a write command, conditions write control logic 38. The decoding of a read command conditions read clock and controls 39. Controls 24 and 38 gate the command from 35 into 29 for serialization to 20 over 19. For a write command, data characters from 14 are gated into 29 by 38 for serialization onto 19. For a read operation, characters received from 20 on 17 are shifted by 39 into read shift register 42. From the latter, they are gated through buffer register 44 onto input bus 15 for ultimate transfer to 10...