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Bit Synchronous Clocking Circuits

IP.com Disclosure Number: IPCOM000093102D
Original Publication Date: 1967-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Harbour, WP: AUTHOR [+2]

Abstract

The system maintains synchronism of a receiver and a transmitter. This is effected by advancing or retarding the phase of the receiver clock, as required, in order to sample data bits at the center. Synchronizing takes place at all times following startup even when no data is being sent. False starts are eliminated.

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Bit Synchronous Clocking Circuits

The system maintains synchronism of a receiver and a transmitter. This is effected by advancing or retarding the phase of the receiver clock, as required, in order to sample data bits at the center. Synchronizing takes place at all times following startup even when no data is being sent. False starts are eliminated.

Two stations are connected for transmission and reception of data, as in drawing A, and include input/output I/O devices 1 and 2 such as printers, magnetic tape transmission units MTXU 3 and 4, and data subsets Mod-Demod 5 and 6. Typical data flow for an individual station is shown in drawing B. False start sequencing is shown in C. A map indicating early and late data bit transitions is shown in D.

Data flow during transmission, drawing B, is from magnetic tape deck 8, shift register 9 with triggers S0...S8, line control 10, and data set 11, to line. During reception, data flow is from one, data set 11, logic 10 and register 9 to deck 8. I/O device 7 is not directly involved in line operations.

Initial startup is achieved by conventional start-stop clocking as shown in the timing sequences in C. The sequences include oscillator, Clock, Valid Start and False Start. When no data is being sent, the line level is high. To start, the line is dropped. To prevent false starts due to noise, etc., the circuits are set to recognize a line drop of minimum duration as shown for Valid Start. A line drop of shorter duration is ignored as shown for False Start. False start circuit 15 depends on signals SDJ, ES, and RS.

Logic 10 operates under control of clock 12 during all operations. C...