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Timing Circuits

IP.com Disclosure Number: IPCOM000093128D
Original Publication Date: 1967-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Boggs, B: AUTHOR [+3]

Abstract

Each circuit in drawings A and D provides an output that is initiated when the input is down for a predetermined interval of time. The output is terminated when the input rises. A further circuit is shown in F.

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Timing Circuits

Each circuit in drawings A and D provides an output that is initiated when the input is down for a predetermined interval of time. The output is terminated when the input rises. A further circuit is shown in F.

The circuit in A operates according to the timing conditions of drawings B and
C. The circuit includes transistors T1...T5, capacitor 1, and voltage points V1 and V2. The output is normally down when the input level is up. T1 turns off any time the input drops. Capacitor 1 starts charging and the voltage at terminal V1 rises exponentially. After a predetermined charging interval t, T2 comes on, turns T3 and T4 off. The level at terminal V2 drops, due to the discharge of capacitor 1. T5 turns off during this interval when point V2 drops to supply the output level indicated.

The circuit in D operates in comparable fashion with some differences in components and circuit interconnections. Initiation and reset are controlled by transistor T1. Timing is controlled by capacitor 2 and transistor T2. Transistors T3, T4, and T5 serve as output.

When the input is up, T1 is on, T2 is off, and the output is down. When the input drops, as in E, T1 turns off. Capacitor 2 begins charging and point V1 starts an exponential rise. When V1 equals V2 plus the turnon voltage of T2 and diode 3, T2 turns on, V3 drops, T5 turns off and the output goes up. If the input rises anytime before T2 turns on, capacitor 2 discharges through resistor 4. T1 and T2 remain off...