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Self Decoding Comparator Circuit

IP.com Disclosure Number: IPCOM000093129D
Original Publication Date: 1967-May-01
Included in the Prior Art Database: 2005-Mar-05
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Woodman, GR: AUTHOR

Abstract

Pairs of transistor circuits, arranged in parallel, provide, at terminals 10, 12, 14, and 16, an indication of the voltage range of an input signal applied at terminals 18 and 20.

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Self Decoding Comparator Circuit

Pairs of transistor circuits, arranged in parallel, provide, at terminals 10, 12, 14, and 16, an indication of the voltage range of an input signal applied at terminals 18 and 20.

There are N stages of transistor pairs, such as pair 22, comprising first and second transistors 24 and 26. Collector 28 of transistor 24 in the Nth stage is connected to collector 30 of the second transistor 32 in the N - 1 stage, and so on. Emitters 34 and 36 of transistors 24 and 26 are coupled as a long-tailed pair differential amplifier, as are the emitters of the first and second transistors in all stages.

The base of the first transistor in each stage is connected to terminal 18 through common connection 37. The base of the second transistor in each stage is connected to one tap in a voltage divider comprising resistors 40, 42, 44, and
46. Precision reference voltage 38 is supplied to the first comparison stage 22 and the voltage divider. Logic voltage is supplied from supply 48 to the collector load resistors 50...54 in each stage.

In operation, an input voltage is supplied across the base of the first transistor in each stage via connection 37. At the same time, a reference voltage is supplied across the base of the second transistor in each stage via connection 39 and the voltage divider comprising resistors 40, 42, 44, and 46. This circuitry effects an absolute comparison between the input voltage and the reference voltage at a given stage. Th...