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Solid State Electroluminescent Display and Scanning Apparatus

IP.com Disclosure Number: IPCOM000093130D
Original Publication Date: 1967-May-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 60K

Publishing Venue

IBM

Related People

Lynch, RJ: AUTHOR

Abstract

Display panel 10 has a plurality of discreet solid state electroluminescent elements 11. The latter are arranged in a two-dimensional matrix array having columns A...E and rows I...V. Each element 11 is essentially a capacitor which luminesces when energized by an AC signal of predetermined amplitude. One type of element 11 comprises zinc sulfide phosphor which has a luminescent signal level of 300 volts AC. Elements 11 in the various rows and colums are selectively and sequentially energized by coincident AC voltage signals. The latter are applied in a manner similar to the technique for scanning a cathode ray tube.

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Solid State Electroluminescent Display and Scanning Apparatus

Display panel 10 has a plurality of discreet solid state electroluminescent elements 11. The latter are arranged in a two-dimensional matrix array having columns A...E and rows I...V. Each element 11 is essentially a capacitor which luminesces when energized by an AC signal of predetermined amplitude. One type of element 11 comprises zinc sulfide phosphor which has a luminescent signal level of 300 volts AC. Elements 11 in the various rows and colums are selectively and sequentially energized by coincident AC voltage signals. The latter are applied in a manner similar to the technique for scanning a cathode ray tube.

Vertical or row scanning of panel 10 is achieved by sequentially turning on PNP transistors 12...16 using a linear DC ramp voltage from a variable DC source 17 connected to the emitter of transistor 12. Each transistor 12...16 is connected in a common base mode amplifier configuration with the collectors connected by wires 18...22 to rows I...V. The base junctions of transistors
12...16 are connected to the emitter of the successive transistors. The base of transistor 16 is connected through current limiting resistor 23 to ground. Turnon and saturation levels of transistors 12...16 are set by resistors 24. Bias level of transistors 12...16 is set with battery 25 connected to resistors 26.

Horizontal or column scanning of panel 10 is achieved by sequentially turning on NPN transistors 27...31. Each horizontal scan transistor 27...31 is connected in a common base mode amplifier configuration with their collectors connected by wires 32...36 to the discreet elements 11 in columns A...E. Transistors 27...31 are sequentially turned on by a linear ramp voltage generated by variable DC source 37 applied to the emitter of transistor 27. Resistors 38 in the emitter circuits of transistors 27...31 set the turnon and saturation levels of the transistors
27...31. Bias is provided by battery 39 connected to collector resistors 40.

For vertical scan, a negative going ramp voltage from source 17 turns on transistor 12 causing the AC voltage signal from AC source 41 to be amplified to one-half the AC voltage level required to cause elements 11 in row I to luminesce. While vertical scan transistor 12 is turned on, hori...