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# Parity Prediction

IP.com Disclosure Number: IPCOM000093155D
Original Publication Date: 1967-Jun-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 41K

IBM

## Related People

Litwak, M: AUTHOR [+3]

## Abstract

In large-size fast adders, particularly for floating point additions, it is necessary that the exponent of the sum and the parity of the exponent be available for gating out with the fraction digits. The exponent cannot be updated to account for normalizing shifts of the fraction sum until after the sum bits are generated and the leading zero digits decoded. Thus the exponent and its parity must be generated in a minimum number of levels of logic.

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Parity Prediction

In large-size fast adders, particularly for floating point additions, it is necessary that the exponent of the sum and the parity of the exponent be available for gating out with the fraction digits. The exponent cannot be updated to account for normalizing shifts of the fraction sum until after the sum bits are generated and the leading zero digits decoded. Thus the exponent and its parity must be generated in a minimum number of levels of logic.

The exponent of the operands being added is shown as held in seven bit positions of exponent register 1. This also stores the sign bit of the fraction in an eighth bit position. When the fraction digits of the sum are generated in the adder not shown, the digits are decoded for normalization in shift decoder 2. The latter can select a right shift of one four-bit digit, no shift, or a left shift of 1...13 four-bit digits. The exponent bits in register 1 are updated in exponent update adder 3 by addition of a seven-bit update amount from decoder 2 on bus 4. A right shift and a zero shift are transmitted on bus 4 as a true binary number. A left shift is transmitted as a 2's complement. Since any shift of up to thirteen digits can be indicated by not more than four bits, the three high-order bits of the update amount are always the same, either all 0's or all 1's. The updated exponent is sent out on seven-bit bus 5 for buffering with the generated fraction.

The predicted parity of the exponent byte including the sign bit is generated from the two input quantities to adder 3, in time to be outgated to the buffers with the updated exponent and sign byte. The four low exponent bits from register 1 pass over bus 6 to a four-input Exclusive-Or 7 which generates an odd parity bit for those four bits. Decoder 2 provides a seven-line bus 8, one line for each decoded shift which has an odd parity for the four low digits as applied on bus 4 to the input of adder 3. These lines are Ored in circuit 9 to generate a signal when the parity of the fou...