Browse Prior Art Database

Asynchronous Control of Data Transfer

IP.com Disclosure Number: IPCOM000093159D
Original Publication Date: 1967-Jun-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 55K

Publishing Venue

IBM

Related People

Jenkins, HE: AUTHOR [+2]

Abstract

The apparatus transfers data between nonsynchronized terminals 10 and 11 via a series of asynchronously operated buffers 12, 13, and 14. The transfer of data is under the control of latches 15...20. These detect which buffer of the three is full and which is empty. Data is received from terminal 10 into buffer 12 and stepped ahead to the last open buffer. Data is transmitted from buffer 14 to receiving system 11 and the following data stepped ahead one buffer.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 46% of the total text.

Page 1 of 3

Asynchronous Control of Data Transfer

The apparatus transfers data between nonsynchronized terminals 10 and 11 via a series of asynchronously operated buffers 12, 13, and 14. The transfer of data is under the control of latches 15...20. These detect which buffer of the three is full and which is empty. Data is received from terminal 10 into buffer 12 and stepped ahead to the last open buffer. Data is transmitted from buffer 14 to receiving system 11 and the following data stepped ahead one buffer.

If control latches 15 and 16 are both off, buffer 12 is empty and available to receive data. If control latches 17 and 18 are off, buffer 13 is empty. If control latches 19 and 20 are off, buffer 14 is empty. If latch 16 is on, buffer 12 is full and the data in it is available for transfer to buffer 13. Likewise, if latch 18 is on, buffer 13 is full. If latch 20 is on, buffer 14 is full.

Data appearing on bus 10 is transferred into buffer 12 under the control of a load pulse appearing on line 21 from the transferring system. Data is transferred to the receiving system on bus 11 under the control of a transfer pulse on line 22 generated by the receiving system.

Assuming that all buffers are empty and all control latches are off, data can be transmitted on bus 10 together with a load signal on line 21 from the transmitting system. Since latch 16 is off, its off output operates one side of And
23. The latter gates the load pulse to form pulse A. This operates gate 24, transmitting the data to buffer 12. Pulse A also sets latch 15 and is inverted by Inverter 25 to inhibit And 26. As latch 15 is set on, its on output comprises one input to And 26. When the load signal on line 21 drops, one input to And 23 is removed, thus turning off the A signal which is inverted to provide the second input to And 26. And 25 sets latch 16. The latter thus provides its on output to one input to And 27, indicating that the data in buffer 12 is ready to be transmitted forward.

Latch 17 is off so that no input is provided to delay 28 and Inverter 29 which provides another input to And 27, Latch 18 is also off and its off output provides a third input to And 27. Such produces output B. This B output operates gate 30 to transmit the data from buffer 12 to buffer 13, resets latch 15, is inverted by Inverter 31 to inhibit And 31 and is inverted by Inverter 33 to inhibit And 34. As latch 15 is reset off, its off output provides one input to And 32. As latch 17 is turned on, the on output provides one input to And 34. After a delay introduced by delay 28, the on output from latch 17 is transmitted to Inverter 29. This removes one input from And 27, turning off the B signal. The B signal, in turning off, is inverted by Inverter 31 to provide the second input to And 32, turning off latch 16. The B signal, in turning off, is also inverted by Inverter 33 to provide the second input to And 34, thus turning on latch 18.

The operation of latch 18 provides the on output to on...