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Deskewing System for Parallel Recorded Data

IP.com Disclosure Number: IPCOM000093160D
Original Publication Date: 1967-Jun-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 76K

Publishing Venue

IBM

Related People

Gindi, AM: AUTHOR

Abstract

The apparatus deskews parallel data to transmit it in nearly exact synchronism. The system is capable of correcting a skew of up to four microseconds to an accuracy of twenty-five nanoseconds. Levels of tapped delay lines of coarse, medium and fine increments are decoded and gated to provide a deskewed readout.

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Deskewing System for Parallel Recorded Data

The apparatus deskews parallel data to transmit it in nearly exact synchronism. The system is capable of correcting a skew of up to four microseconds to an accuracy of twenty-five nanoseconds. Levels of tapped delay lines of coarse, medium and fine increments are decoded and gated to provide a deskewed readout.

Deskewing is achieved through several levels of delay lines. Coarse delay line 10 contains seven microseconds of delay tapped at one microsecond intervals. The even and odd outputs of delay 10 are gated respectively by even gate 11 and odd gate 12 to even medium delay line 13 and odd medium delay line 14. Delays 13 and 14 comprise 875 nanoseconds of delay tapped at 125 nanosecond intervals. The even and odd outputs of delays 13 and 14 are gated respectively by even gate 15 and odd gate 16 to even fine delay line 17 and odd fine delay line 18 respectively. Delays 17 and 18 comprise a delay of 100 nanoseconds, tapped at 25 nanosecond intervals. The outputs of delays 17 and 18 are connected to output gate 19. The latter is controlled by fine ring counter
20. Gates 15 and 16 are controlled by medium ring counter 21. Gates 11 and 12 are controlled by coarse ring counter 22.

Initial control of the deskewing logic of drawing 1 is made by the synchronizing logic of drawing 2. Trigger 23 is initially set by the start record pulse appearing on line 24. Operation of trigger 23 initiates a start gate signal on line 25 which operates initial starting circuit 26 of drawing 1.

Initially, ring counters 20, 21, and 22 are set for zero delay.

At this time, a start signal on line 25 initiates circuit 26 and the first bit of each track is gated into the corresponding delay line system, including the synchronizing track. The first bit for each data track appears at a corresponding input line 27. The first bit of the sync track data appears at input 28 in drawing 2. The sync track data is delayed for four microseconds by delay line 29. This amount of delay is one half of that of the read data delay capability as shown in drawing 1. Hence, for the case where there is no skew, the sync pulse appears at the output of delay 29 at the same moment that the read data pulse appears at the four microsecond output of delay 10. The system of drawing 1 thus accommodates skew up to four microseconds either side of the sync data.

During the start gate period, the first sync pulse is gated into delay 29 and the read data is gat...