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Dynamic Processor Allocation in Multiprocessing System

IP.com Disclosure Number: IPCOM000093169D
Original Publication Date: 1967-Jun-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Berkling, K: AUTHOR

Abstract

In this system, a control processor controls a plurality of other processors. The control processor executes only control instructions. The other processors are capable of executing all but control instructions. With such arrangement, dynamic multiprocessing is enabled with a minimizing of programming and circuitry. The control processor can also control input/output channels.

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Dynamic Processor Allocation in Multiprocessing System

In this system, a control processor controls a plurality of other processors. The control processor executes only control instructions. The other processors are capable of executing all but control instructions. With such arrangement, dynamic multiprocessing is enabled with a minimizing of programming and circuitry. The control processor can also control input/output channels.

In such arrangement of a plurality of processors coordinated by a control processor, the compiler has a program partitioned into a group of program pieces of serial code. All pieces are terminated by a stop instruction. The compiler represents such group by a list of pointers to the origins of the program pieces. The control processor dynamically assigns the other processors to execute the program pieces. Such procedure is controlled by a program busy register. The latter has a capacity of n bits, one for each controlled processor. A given register bit is set to a 1 when a chosen controlled processor is assigned to execute a particular program piece. A given register bit is reset to a 0 when it encounters the stop instruction of the program piece.

A cyclic counter is included which is stepped once in a basic machine cycle. The current value of this counter addresses a controlled processor and its corresponding bit in the processor busy register and denotes a time slot for memory access. After an instruction counter of the coordinator is advanced and the instruction word is fetched, further action is suppressed. Such occurs until the cyclic counter addresses a 0 bit in the processor busy register indicating an idle controlled processor a...