Browse Prior Art Database

IGFET Decoders and Encoders

IP.com Disclosure Number: IPCOM000093185D
Original Publication Date: 1967-Jun-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Launduaer, RW: AUTHOR

Abstract

The decoder arrangement comprises a plurality of spaced parallel p-type diffusions formed in an N-type semiconductive wafer W. Surface The decoder arrangement comprises a plurality of spaced parallel P-type diffusions formed in an N-type semiconductive wafer W. Surface portions of wafer W intermediate corresponding source and drain diffusions S and D define input channels C of logical Nor elements. Diffusions S are connected to ground along common diffusion A. diffusions D are connected along individual load resistors R to operating potential B+. A thin insulating layer, not shown, is formed over diffusions S and D. Selected surface portions of diffusions S and D, registered over input channels C, are of reduced thickness.

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IGFET Decoders and Encoders

The decoder arrangement comprises a plurality of spaced parallel p-type diffusions formed in an N-type semiconductive wafer W. Surface The decoder arrangement comprises a plurality of spaced parallel P-type diffusions formed in an N-type semiconductive wafer W. Surface portions of wafer W intermediate corresponding source and drain diffusions S and D define input channels C of logical Nor elements. Diffusions S are connected to ground along common diffusion A. diffusions D are connected along individual load resistors R to operating potential B+. A thin insulating layer, not shown, is formed over diffusions S and D. Selected surface portions of diffusions S and D, registered over input channels C, are of reduced thickness.

A plurality of gate electrodes G is formed over surface portions of the insulating layer of reduced thickness which, when biased, support conduction along corresponding input channels C. A plurality of metallic conductors M is formed over insulating layer and connected to selected gate electrodes G. The remaining gate electrodes G are connected to corresponding diffusions S, i. e., ground, along via holes in the insulating layer. Output conductors O are connected to each diffusion D through other via holes in the insulating layer. Logical inputs, as illustrated, when applied along conductors M, are operated upon by the logical Nor elements. Such operations are reflected by voltage changes along particular output cond...