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Integrated Fast Read, Slow Write Memory Cell Using Insulated Gate Field Effect Transistors

IP.com Disclosure Number: IPCOM000093188D
Original Publication Date: 1967-Jun-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Keller, WL: AUTHOR

Abstract

The memory cell in drawing A affords nondestructive readout operation with only two array lines. The latter perform all the necessary drive and sense functions for both reading and writing. All circuit components are field-effect transistors. The memory cell is able to distinguish a read pulse from a write pulse based on pulse width and amplitude. Drawing B shows the pulse patterns for both word line 10 and bit-sense line 12 for the various conditions of reading and writing binary 1's and binary 0's. The third curve shows the potential appearing at point 8 at side M of the cell during the various storage conditions of the cell.

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Integrated Fast Read, Slow Write Memory Cell Using Insulated Gate Field Effect Transistors

The memory cell in drawing A affords nondestructive readout operation with only two array lines. The latter perform all the necessary drive and sense functions for both reading and writing. All circuit components are field-effect transistors. The memory cell is able to distinguish a read pulse from a write pulse based on pulse width and amplitude. Drawing B shows the pulse patterns for both word line 10 and bit-sense line 12 for the various conditions of reading and writing binary 1's and binary 0's. The third curve shows the potential appearing at point 8 at side M of the cell during the various storage conditions of the cell.

Reading and writing are performed by applying positive pulses to line 10 and line 12, drawing A. If a positive pulse with sufficient amplitude and width is applied to lines 10 and 12 simultaneously, shown by the pulses in curves 1 and 2 between times t2 and t3, a current flows from line 12 through write gate 14 and the cell to ground. This current flow causes the drain voltage at side A of the cell to rise above its threshold voltage, allowing side M, i. e., point 8 to switch to the high-voltage state.

If a read pulse is now applied to line 10, i. e., curve 1 between times t3 and t4, it appears as a signal on line 12. This is because read gate 16 has been biased in the low-impedance state by side M of the cell. The read pulse is of insufficient heigh...