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Browse Prior Art Database

Monolithic Semiconductor Packaging Arrangement

IP.com Disclosure Number: IPCOM000093193D
Original Publication Date: 1967-Jun-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Agusta, B: AUTHOR [+3]

Abstract

This monolithic semiconductor packaging arrangement is for mounting and interconnecting a large number of integrated semiconductor chips on a common carrier.

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Monolithic Semiconductor Packaging Arrangement

This monolithic semiconductor packaging arrangement is for mounting and interconnecting a large number of integrated semiconductor chips on a common carrier.

In drawing A, an integrated semiconductor chip has insulated through-holes comprised, preferably, of a thermal oxide or other form of insulation lined openings. The latter are encircled by device contact metallurgy regions. These provide electrical contact to the devices contained in the integrated semiconductor chip.

In drawing B, another arrangement utilizes a slotted chip configuration with slots formed around the edge of the chip rather than using through-holes through the chip as in drawing A. The insulation in both devices provides the support surface for metal conducting bus bars, not shown, which provide electrical connection from chip to chip. Openings, selectively provided in the insulating layer, permit electrical connection between the contact metallurgy and the bus bars. In this manner, a number of these chips having, for example, monolithic memory circuits, can be mounted on edge of a common chip carrier, thus providing a high-density monolithic package.

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