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Browse Prior Art Database

Phase or Frequency Encoding Circuit

IP.com Disclosure Number: IPCOM000093214D
Original Publication Date: 1967-Jul-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Belcastro, LE: AUTHOR [+2]

Abstract

The circuit is for phase or frequency encoding information that can be used for communication purposes or writing magnetic data. This circuit writes a 0 bit by a pulse, or current switching, at approximately the 90 degree phase position in a bit period T or 1 bit by a pulse, or current switching, at approximately a 270 degree phase position in a bit period T. Only one pulse or switching can occur within a single bit period T. However, there is no pulse or switching in a bit period representing a 0 bit immediately following a 1 bit period.

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Phase or Frequency Encoding Circuit

The circuit is for phase or frequency encoding information that can be used for communication purposes or writing magnetic data. This circuit writes a 0 bit by a pulse, or current switching, at approximately the 90 degree phase position in a bit period T or 1 bit by a pulse, or current switching, at approximately a 270 degree phase position in a bit period T. Only one pulse or switching can occur within a single bit period T. However, there is no pulse or switching in a bit period representing a 0 bit immediately following a 1 bit period.

The data input in the drawing has a 1 bit represented by an up level for a bit period, which might occur for a time interval between clock times 6...6. Similarly an input 0 bit might be represented by a down level for a similar bit period. A 0 bit input level enables latch L1 so that it can be set at 7 clock time, provided latch L2 is in reset status. When set, the output of L1 enables And 23 to cause the generation of a 0 bit represented as a pulse or switching at approximately the 90 degree position within a bit period T. A 1 bit input level enables L2 so that it can be set at 1 clock time.

When set, L2 enables And 24 to control the generation of a 1 bit represented in the output by a pulse or flux switching at approximately 270 degrees in a bit period T.

Only one latch L1 or L2 can be set at any one time. This is caused by the control of reset R on both latches. In such control, L1 is reset by a 1 bit level 5 clock time which occurs before it can be set by a 0 bit at the immediately following 7 clock time. Similarly, L2 is reset by a 0 input level at 8 clock time, which occurs shortly before the time that L2 can be set at 1 clock time by a 1 bit level. The one exception in which neither L1 or L2 is set is in response to a 0 data bit following a 1 data bit input signal.

Whenever set, the off output of L2 provides a disabling input to And
10. If during the following bit period a 0 input level is provided, And 10 is disabled at 7 clock time, which is the only actuation time available to L1 during the 0 input level. Therefore...