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Instruction Prefetching Interlock

IP.com Disclosure Number: IPCOM000093217D
Original Publication Date: 1967-Jul-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 35K

Publishing Venue

IBM

Related People

Anderson, DW: AUTHOR [+3]

Abstract

In data processing systems with extensive overlapped operations, instructions are normally prefetched from storage to a set of buffer registers for later sequential decoding. It is recognized that, if an instruction results in storage of an operand into an instruction word which has already been prefetched, error can arise. Such can occur unless the instruction word is refetched after the operand has been stored. If the instruction decoding is pipelined for performance in several stages, the above type of operation is too slow. This is because an erroneously prefetched instruction may be already in the decoder pipeline before it can be recognized that the instruction has been prematurely fetched.

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Instruction Prefetching Interlock

In data processing systems with extensive overlapped operations, instructions are normally prefetched from storage to a set of buffer registers for later sequential decoding. It is recognized that, if an instruction results in storage of an operand into an instruction word which has already been prefetched, error can arise. Such can occur unless the instruction word is refetched after the operand has been stored. If the instruction decoding is pipelined for performance in several stages, the above type of operation is too slow. This is because an erroneously prefetched instruction may be already in the decoder pipeline before it can be recognized that the instruction has been prematurely fetched.

In the drawing, whenever an instruction resulting in storage of an operand is decoded, Store Op trigger 1 is set as a part of the decoding operation. Simultaneously the storage address at which the operand is to be stored is generated in Address Adder 2. The generated address is passed by Gating Control Circuit 7 into Result Register 3. The Store Op tag bit in Trigger 1 is transferred into Store Op Trigger 4 through And's 5 and 6.

To detect an operation by which an operand is to be stored into an instruction which has already been prefetched from storage and is therefore logically prematurely fetched, Compare Circuit 9 is supplied with the storage address from Register 3. Compare 9 is also supplied from Instruction Address Circuit 10 with the instruction addresses of both the next instruction to be decoded and the last instruction already prefetched from storage. If the storage address in Register 3 is within the range of these instruction addresses, the corresponding instruction word has been prematurely fetched. And 11 is responsive to a signal from Compare 9 indicating that the address comparison found a match and is also responsive to Trigger 4, when set, to send out a signal 12 to the instruction unit notifying it of the premature fetch. Upon receipt of the signal, the instruction unit controls...