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Fused Diode Matrix Fabrication

IP.com Disclosure Number: IPCOM000093246D
Original Publication Date: 1967-Jul-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Drake, GV: AUTHOR [+2]

Abstract

Fused diode matrix fabrication techniques are shown. Such techniques minimize the number of types of monolithic chips which must be produced to perform varied logical functions and they reduce the connection pin requirements.

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Fused Diode Matrix Fabrication

Fused diode matrix fabrication techniques are shown. Such techniques minimize the number of types of monolithic chips which must be produced to perform varied logical functions and they reduce the connection pin requirements.

Drawing A shows a monolithically fabricated semiconductor chip including a diode matrix with fused inputs. Complemented input terminals A, A...N, N are each connected to respective diodes D1...D4 by way of respective fuse links L1...L8 and resistors R1... R8. Diodes D1 have their anodes connected to each other and to output terminal 1 and to a positive supply via a bias resistor. Diodes D2, D3, and D4 are similarly connected.

The desired logical functions are obtained by burning the fuse between each diode and one or both complemented input lines to it. To burn out the fuse L1 between R1 and A, ground potential is applied to A and a voltage V1 is applied to
A. The level of V1 is sufficiently low so that current flow from A through R2 and R1 does not burn out fuse L1. Then a voltage V2 is applied to output 1, V2 being equal to V1 plus the voltage drop across a forward biased diode, e.g., 7v for silicon. The current flow from output 1 through D1, R1, and L1 to A burns out fuse L1. Other fuses are selectively burned out in a similar manner to realize the desired chip circuitry.

In drawing B, a fused diode matrix is terminated on the same chip by Inverters 10, 11, and 12. Inputs A...D are connected to respective di...