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Electron Beam Testing Apparatus for Integrated Circuits

IP.com Disclosure Number: IPCOM000093249D
Original Publication Date: 1967-Jul-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Walker, EJ: AUTHOR [+2]

Abstract

This technique is for testing an integrated sequential logical circuit, comprising insulated gate field-effect transistors IGFET's, using electron beam techniques to set the circuit into a known state independent of the states of circuit inputs so as to defeat feedback loops and allow testing in a combinatorial mode.

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Electron Beam Testing Apparatus for Integrated Circuits

This technique is for testing an integrated sequential logical circuit, comprising insulated gate field-effect transistors IGFET's, using electron beam techniques to set the circuit into a known state independent of the states of circuit inputs so as to defeat feedback loops and allow testing in a combinatorial mode.

In A, the sequential logical circuit to be tested comprises a pair of two-input Nor's I and II in latching arrangement. The respective outputs are coupled along feedback loops 1 and 2 to one input of the other. Circuit I comprises input transistors T1...TN having drains D commoned along resistor R1 to voltage source -B and sources S commoned to ground. Circuit II comprises input transistors T2...TM having drains D commoned along resistor R2 to voltage source -V and sources S commoned to ground.

Output terminal 10 is connected along feedback loop 1 to the gate of T2. Output terminal 20 is connected along feedback loop 2 to the gate of T1. Since T1...TN and T2...TM are enhancement-mode types, i.e., NPN, such transistors are cut off when the respective gates are unenergized, e.g., at ground. Such transistors are on when the respective gates are energized, e.g., at -V. During operation, outputs 10 and 20 are alternately at ground and -V.

In addition, Nor's I and II include testing transistors T3 and T4, respectively, which have adjustable potential gates G of the type shown in B. A gate G is divided...