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Combined Single Shot and Delay Circuit

IP.com Disclosure Number: IPCOM000093254D
Original Publication Date: 1967-Jul-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Hines, HW: AUTHOR

Abstract

The circuit performs the dual function of a single-shot and a delay circuit. It is shown in a PNP field effect transistor configuration. However, an NPN configuration can be used.

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Combined Single Shot and Delay Circuit

The circuit performs the dual function of a single-shot and a delay circuit. It is shown in a PNP field effect transistor configuration. However, an NPN configuration can be used.

Assuming the input to be at ground potential, transistors T1 and T6 are cut off causing points A and B to be negative. With points A and B negative, transistors T3 and T4 conduct and point C is at ground. This condition is stable and continues until the input goes negative, curve A. At this time, T1 and T6 turn on. Transistor T2 is also in conduction since its gate is connected to point B and is negative. When T1 conducts, point A and the single-shot output become positive or at ground as shown in curve B and T4 is cut off causing point C to start going negative. The gate voltage on transistor T5 follows curve C which is determined by resistors R2 and R3 and capacitor C. When the voltage on the gate of T5 becomes sufficiently negative, T5 turns on and point B and the delay circuit output go to ground, as shown in curve D, and cut T2 off. When T2 cuts off, point A and the single-shot output become negative as shown in curve B.

This condition is also stable and prevails until the input rises to ground as shown in curve A. When the input rises to ground, T1 and T6 are cut off. Cutting T1 off has no effect since T2 is off. However, when T6 is cut off, point B becomes negative and the delay circuit output becomes negative as shown in curve D and point C...