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Self Correcting Synchronizable Ring Counter

IP.com Disclosure Number: IPCOM000093284D
Original Publication Date: 1967-Aug-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 29K

Publishing Venue

IBM

Related People

Maasberg, WA: AUTHOR

Abstract

The ring counter output from each flip-flop FF is used, for example, to energize the rows in a row and column memory matrix not shown. A second, similar ring counter, not shown, can be used to energize the columns of the row and column matrix. The Nand's operate to assure that the counter has one and only one FF with a 1 on its Q output at the beginning of each cycle. The Nand's also provide error correction if no 1 is present on any output.

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Self Correcting Synchronizable Ring Counter

The ring counter output from each flip-flop FF is used, for example, to energize the rows in a row and column memory matrix not shown. A second, similar ring counter, not shown, can be used to energize the columns of the row and column matrix. The Nand's operate to assure that the counter has one and only one FF with a 1 on its Q output at the beginning of each cycle. The Nand's also provide error correction if no 1 is present on any output.

Each flip-flop FF 1. .. FF N represents one stage in the N-stage counter. Each flip-flop has a 1 either on its Q output or on its Q output. The output not having a 1 is in the 0 stage. Each flip-flop has set S and reset R inputs along with preset P and clock pulse CP inputs. A 1 applied to the S input along with a clock pulse applied at the CP input sets the Q output to 1. Alternatively, a 1 applied at the R input, when a clock pulse is applied at the CP input, sets the Q to a 1. If an input pulse is applied either to the S or P input, the Q or Q output does not change state unless an input pulse is also applied at the CP input. A preset pulse to input P, however, always sets a 1 in the Q output without the need for a CP input. Output Out 1 from FF 1 is taken from its Q output. Out 2. .
. Out N for FF 2...FF N, respectively, are all taken from the Q outputs.

In operation, a 1 is serially moved from Out 1 to Out 2 . . . Out N and back to Out 1 in completing one cycle. The shift from each outputto the next is under the control of CP signals w here a 1 is shifted one output for each CP applied to the CP inputs.

It is desired to have only one 1 on any Out 1...Out N at any one time. A ring counter of N-stages, as shown, however, inherently has a capability of 2/N/ possible states if any combination of outputs is permitted. Since it is desired to have only one 1, then only N of those 2/N/ states are desired. Because of the large number of possible states other than just N, the counter can accidentally fall into an incorrect state when it is initially turned on or if it is disturbed during a cycle. The three Nand's function first to reset the counter each cycle to an initial state in which FF 1 has the only output 1, second to reset to the initial state if none ofthe FF 2...FF N have a 1 output, and third to reset to the initial state upon receipt of an external sync input signal.

For example, if FF N-1 has a 1 on its Q output so that only Out N-1 output has a 1, receipt of a CP signal causes FF N to switch a 1 from its Q output to its Q output since the Q output...