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Browse Prior Art Database

Digitally Programmable Derived Clock

IP.com Disclosure Number: IPCOM000093285D
Original Publication Date: 1967-Aug-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Deutsch, H: AUTHOR [+4]

Abstract

The circuit produces a preselected frequency from a given range of frequencies from a digital address related to the desired frequency. A binary constant from any convenient source and the digital address corresponding to the desired frequency are summed in sigma. The sum is divided in the computing register into a preset number which equals one half the frequency of a fixed oscillator. The quotient thus derived is inserted into a register and is numerically equal to one half the period of the desired frequency.

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Digitally Programmable Derived Clock

The circuit produces a preselected frequency from a given range of frequencies from a digital address related to the desired frequency. A binary constant from any convenient source and the digital address corresponding to the desired frequency are summed in sigma. The sum is divided in the computing register into a preset number which equals one half the frequency of a fixed oscillator. The quotient thus derived is inserted into a register and is numerically equal to one half the period of the desired frequency.

The fixed oscillator operates a counter. A comparison circuit responsive to the quotient register and the counter triggers a flip-flop upon a determination of equality. The triggering pulse is also utilized to reset the counter which again counts to equality, at which time the flip-flop is triggered to its opposite state.

Thus the flip-flop is toggled at a rate equal to one half the period of the desired frequency. Its output is therefore the desired frequency.

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