Browse Prior Art Database

Capacitance Tester with Digital Readout

IP.com Disclosure Number: IPCOM000093286D
Original Publication Date: 1967-Aug-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Albert, KP: AUTHOR

Abstract

Shown at A is a block diagram of a tester for measuring junction capacitance of semiconductors attached to associated circuitry not shown. The tester includes oscillator 1 whose output is coupled through test capacitor Cx to the input of operational amplifier 2 having feedback 3 to its input through known capacitance C. The output of amplifier 2 is fed to the input of amplifier 4 having its output connected to AC peak detector 5 for reading in digital voltmeter DVM 6.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 73% of the total text.

Page 1 of 2

Capacitance Tester with Digital Readout

Shown at A is a block diagram of a tester for measuring junction capacitance of semiconductors attached to associated circuitry not shown. The tester includes oscillator 1 whose output is coupled through test capacitor Cx to the input of operational amplifier 2 having feedback 3 to its input through known capacitance C. The output of amplifier 2 is fed to the input of amplifier 4 having its output connected to AC peak detector 5 for reading in digital voltmeter DVM 6.

In accordance with the theory of operation, the expression for voltage E2 at the output of amplifier is E2= Ein Z feedback/Z input where Z input = 1/Jw Cx and Z feedback = 1 /JwC. Thus, E2 = Ein (1/JwC)/(1/Jw Cx) which reduces to E2 = Ein Cx/C.

The gain of amplifier 4 is Ck/Ein where k is the dimensioning constant of amplifier 4. The output of amplifier 4 is E4 = E2 x gain = Ein CxCk/C Ein = k Cx volts. An AC peak detector 5 then converts the 1 MC signal to DC for display on DVM 6.

Shown in B is an alternative tester for measuring low Q capacitors or low Q semiconductor junction capacitances. A low Q is, by definition, shunted by a low value resistor.

As above, this arrangement includes oscillator 1 whose output is coupled through a resistor Rx-shunted, test capacitor Cx to the input of operational amplifier 2. The latter has a feedback 3 to its input through a known capacitance
C. The output of amplifier 2 is fed to the input of amplifier 4 having its output ...