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No Ripple Binary Counter with Latch Implementation

IP.com Disclosure Number: IPCOM000093288D
Original Publication Date: 1967-Aug-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Dieffenderfer, JW: AUTHOR

Abstract

A binary counter having n stages has 2/n/ different states. For example, seven-stage counter 100 has 2/7/ = 128 different states which represent the binary numbers 0000000...1111111. Initially, the counter is cleared by a reset pulse R' applied to an appropriate reset terminal not shown. A signal Z provides sequential incrementing pulses Z1, Z2, etc., for stepping the counter. The latter operates on the basis of two principles. First, application of each pulse from signal Z to the counter causes the low-order stage 20 to change state. Secondly, if a stage of the counter changes from a 1 to a 0 state, the state of the next higher order stage of the counter is complemented. However, if the stage changes from a 0 to a 1 state, the state of the next higher order stage remains unchanged.

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No Ripple Binary Counter with Latch Implementation

A binary counter having n stages has 2/n/ different states. For example, seven-stage counter 100 has 2/7/ = 128 different states which represent the binary numbers 0000000...1111111. Initially, the counter is cleared by a reset pulse R' applied to an appropriate reset terminal not shown. A signal Z provides sequential incrementing pulses Z1, Z2, etc., for stepping the counter. The latter operates on the basis of two principles. First, application of each pulse from signal Z to the counter causes the low-order stage 20 to change state. Secondly, if a stage of the counter changes from a 1 to a 0 state, the state of the next higher order stage of the counter is complemented. However, if the stage changes from a 0 to a 1 state, the state of the next higher order stage remains unchanged.

In accordance with the two principles, as the n-stage counter changes from one of its 2/n/ states to the next state in response to the incrementing pulses, it does so in one of n+1 ways W. Table 1 indicates the action which results to each stage and which is associated with each of the particular n+1 ways W1, W2, etc.

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In Table 1, the characters S and R indicate that the particular stages are set to a 1 state and reset to a 0 state, respectively. Their absences indicate that the state of the particular stage remains unchanged. Thus, seven-stage counter 100 has n+1 = 8 possible ways W1... W8 of changing from one of its 128 states to the next. In regards to way W8 for the particular seven-stage example, all seven stages are reset to the 0 state.

In accordance with the two principles and after counter 100 is cleared by pulse R', the first incrementing pulse Z1 causes the low-order stage 2/0/ to change from a 0 state and to be set to a 1 state. As a result, the next higher order stages 2/1/, etc., do not change states and the action corresponds to way W1. The second incrementing pulse Z2 causes the low-order stage 2/0/ to change from a 1 to a 0 state. As a result stage 2/1/ is complemented and goes from a 0 to a 1 state. However, the higher order stages 2/2/, etc., remain in their 0 states. The action resulting from the application of pulse Z2 corresponds to way W2.

Application of pulse Z3 causes stage 2/0/ to be set to a 1 and consequently the states of the higher order stages 2/1/, etc., remain unchanged and the action corresponds to way W1. Application of the pulse Z4 resets stage 2/0/ to a 0 state causing stage 21 to be complemented. As a result stage 2/1/ changes from a 1 to a 0 state thus causing the next higher order stage 2/2/ to be complemented in turn. Since stage 2/2/ changes from a 0 to a 1 state, the next higher stages 2/3/, etc., do not change states. Application of pulse Z4 produces an action corres...