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Selective Annealing of Memory Film Devices

IP.com Disclosure Number: IPCOM000093315D
Original Publication Date: 1967-Aug-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Louis, HP: AUTHOR

Abstract

Continuous film memory devices are selectively annealed to give a high wall coercive force H and a high dispersion proportional to in the magnetic material between the storage locations while maintaining a low H and proportional to within the storage cells. This is done by annealing the memory plane while the storage cells are magnetized in the easy axis and the magnetic material between the storage cells is magnetized in the hard axis. During the annealing process, H and proportional to increase in the magnetic material between the storage locations as is desired, while the lower Hc and proportional to are maintained in the storage cells.

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Selective Annealing of Memory Film Devices

Continuous film memory devices are selectively annealed to give a high wall coercive force H and a high dispersion proportional to in the magnetic material between the storage locations while maintaining a low H and proportional to within the storage cells. This is done by annealing the memory plane while the storage cells are magnetized in the easy axis and the magnetic material between the storage cells is magnetized in the hard axis. During the annealing process, H and proportional to increase in the magnetic material between the storage locations as is desired, while the lower Hc and proportional to are maintained in the storage cells.

Desirably, the film is magnetized prior to the annealing treatment by locking the whole plane in the hard axis. Then only the storage cells are reset into the easy axis by writing a 1 or a 0 into them. The film can then be annealed at elevated temperatures, for example, 200 degrees C for 60 minutes.

Use of the selective annealing method decreases word line impedance from magnetic loading in the unused film under the word lines while maintaining lower dispersion in the storage cells. The method also decreases creep sensitivity of the storage cells caused by creepout and interaction between neighboring bit locations.

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