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High Speed Transistor

IP.com Disclosure Number: IPCOM000093331D
Original Publication Date: 1967-Aug-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Lloyd, RH: AUTHOR

Abstract

In a high-speed transistor it is desirable to maintain a low ratio of collector area to emitter area and a high collection efficiency of carriers from the emitter sidewall in order to reduce the charge stored in the base region. Thus the frequency response and DC gain of the transistor are increased. This device reduces the size of the collector. This is effected by elimination of the extra area normally required to accommodate misalignment of the mask used to perform the base diffusion.

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High Speed Transistor

In a high-speed transistor it is desirable to maintain a low ratio of collector area to emitter area and a high collection efficiency of carriers from the emitter sidewall in order to reduce the charge stored in the base region. Thus the frequency response and DC gain of the transistor are increased. This device reduces the size of the collector. This is effected by elimination of the extra area normally required to accommodate misalignment of the mask used to perform the base diffusion.

A first base diffusion is performed through hole 1 in oxide layer 2 to provide base portion 3. A second hole 4 is then cut in oxide 2 and a second base diffusion is performed. In this case, the width and depth of the diffusion are somewhat greater than those performed in the first base diffusion step. The resulting base is made up of area 3 from the first base diffusion and area 5 from the second base diffusion.

The thin layer of oxide which forms during the second base diffusion in the area of hole 4 is then removed by a dip etch to reopen hole 4. The emitter diffusion is then performed through the same hole as is the second base diffusion. The oxide coating over hole 4 is then removed by a second dip etch process. The device is completed by the addition of plated contact 6 for the collector region, contact 7 for the base region, and contact 8 for the emitter region. The surface oxide is not shown on the completed device.

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