Browse Prior Art Database

Three Phase Information Exchange

IP.com Disclosure Number: IPCOM000093378D
Original Publication Date: 1967-Sep-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Schwartz, JT: AUTHOR

Abstract

This information exchange routes addresses and data between 2/n/ processing units and 2/n/ buses which comprises n+1 successively disposed ranks of registers. Each rank consists of 2/n/ individual registers. Words of data including n-bit destination bus addresses are entered into the n/th/, highest, rank of registers from which they advance through successive ranks to the registers of the 0/th/, lowest, rank. The words are descendingly advanced from rank to rank on successive clock phases provided that the register in the next rank to which a word is to be transmitted is empty of data.

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Three Phase Information Exchange

This information exchange routes addresses and data between 2/n/ processing units and 2/n/ buses which comprises n+1 successively disposed ranks of registers. Each rank consists of 2/n/ individual registers. Words of data including n-bit destination bus addresses are entered into the n/th/, highest, rank of registers from which they advance through successive ranks to the registers of the 0/th/, lowest, rank. The words are descendingly advanced from rank to rank on successive clock phases provided that the register in the next rank to which a word is to be transmitted is empty of data.

Three clock phases are provided, each having a length of a chosen amount of logical delay times, suitably two of such times. The clock phases occur repetitively cyclically, i.e., first clock phase, second clock phase, third clock phase, first clock phase, etc.

The configuration of the clock pulses is arranged such that, during each clock phase, a given register of a rank is either receiving information from a specific register of the next higher rank or is transmitting information to one of two chosen registers of the next lower rank. As a transmitted data word and its associated destination address enters a rank, the corresponding bit of the destination address for that rank is decoded to determine to which of two possible destination registers in the next lower rank a given register is to transmit.

There are shown the transmitting and receiving patterns for a three phase information exchange comprising four ranks of registers, each rank containing e...