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Sequential Turnon Order of Detecting Circuit

IP.com Disclosure Number: IPCOM000093380D
Original Publication Date: 1967-Sep-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Maholick, AW: AUTHOR [+2]

Abstract

This circuit determines the turnon order of a plurality of inputs to it. Three inputs 1, 2 and 3 are shown. However, the circuit can be expanded to include any number of inputs. The circuit employs three-state latches 10, 11, and 12. Each latch includes an X state, a Y state, and an R or reset state. Initially, a start reset pulse is applied to the R state of each latch 10, 11, and 12. The output of the R state enables a plurality of And's at the inputs to the X and Y states, respectively. The 1 and 2 inputs to the circuit are connected to the first pair of And's associated with the X and Y states of latch 10. If the first input occurs prior to either the second or the third input, latch 10 is set to the X state and thus indicates that the first input line occurs prior to the second input line.

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Sequential Turnon Order of Detecting Circuit

This circuit determines the turnon order of a plurality of inputs to it. Three inputs 1, 2 and 3 are shown. However, the circuit can be expanded to include any number of inputs. The circuit employs three-state latches 10, 11, and 12. Each latch includes an X state, a Y state, and an R or reset state. Initially, a start reset pulse is applied to the R state of each latch 10, 11, and 12. The output of the R state enables a plurality of And's at the inputs to the X and Y states, respectively. The 1 and 2 inputs to the circuit are connected to the first pair of And's associated with the X and Y states of latch 10. If the first input occurs prior to either the second or the third input, latch 10 is set to the X state and thus indicates that the first input line occurs prior to the second input line. As soon as latch 10 switches to the X state, the reset state terminates. The two And's connected to the X and Y states of latch 10 are disabled, thus preventing a subsequent input from effecting latch 10.

Similarly, the 1 and 3 inputs are connected through a pair of And's to the X and Y states, respectively, of latch 11. The 2 and 3 inputs are connected through a pair of And's in the same manner to the X and Y states of latch 12. An And is connected to the X state of latch 10, to the X state of latch 12 and directly to the 3 input to indicate that the 1st, 2nd and 3rd inputs occur in that order. The remaining five output And's a...