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Parallel Bidirectional Counter

IP.com Disclosure Number: IPCOM000093381D
Original Publication Date: 1967-Sep-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Maholick, AW: AUTHOR [+2]

Abstract

This counter increments or decrements a count, stored in parallel in a storage register. The logic for four stages of the bidirectional counter is shown. The storage registers and the arrangement for transferring the data from the storage registers to the logic and to the output are not shown.

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Parallel Bidirectional Counter

This counter increments or decrements a count, stored in parallel in a storage register. The logic for four stages of the bidirectional counter is shown. The storage registers and the arrangement for transferring the data from the storage registers to the logic and to the output are not shown.

The logic in the drawing is an implementation of the equations set forth below. The equations are derived from a Karnaugh mapping of the next state or count as a function of the present state of count and whether the command to increment, i.e., add 1 or decrement subtract 1, is previously issued.

(Image Omitted)

Further simplification is possible. This is not shown since the iterative structure implemented by the equations is stressed. The circuit is expanded to include more stages since the iterative build-up, indicated by the general equation, can be carried out as above.

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