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Unijunction Transistor Storage Cell

IP.com Disclosure Number: IPCOM000093444D
Original Publication Date: 1967-Sep-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Gillet, JB: AUTHOR

Abstract

This is a single unijunction transistor storage cell. Emitter E of the transistor is connected through a load resistor R to a word line Vw. One base B1 of the transistor is connected to a bit line Vb. The other base B2 is connected to a source of reference potential shown as ground.

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Unijunction Transistor Storage Cell

This is a single unijunction transistor storage cell. Emitter E of the transistor is connected through a load resistor R to a word line Vw. One base B1 of the transistor is connected to a bit line Vb. The other base B2 is connected to a source of reference potential shown as ground.

To read the information stored in the cell, the potential on line Vw is increased causing a pulse to be transmitted to line Vb depending on whether or not a 1 or 0 is stored. To write information into the cell, the cell is first reset by decreasing the Vw potential. If a 1 is to be stored, a negative-going pulse is therefore applied to line Vb concurrently with the positive-going pulse to line Vw. If a 0 is to be stored, the potential on line Vb is retained at the quiescent potential while the potential on line Vw is increased.

In monolithic form, the storage cell has wafer 1 of N-type conductivity in which is formed an annular emitter region 2 of P-type conductivity. Region 3 of P- type conductivity extends from emitter region 2 and constitutes the load resistor
R. Region 5 of N/+/ conductivity surrounds all the emitter regions on the slice. Region 4 of N/+/ conductivity corresponding to B1 is formed within annular emitter region 2. Insulating film 11 is provided over the surface of the slice and conductive strips 12 and 14 are formed on the film 11 to constitute the Wb lines respectively. Conductive material 15 is deposited over region 5 in apertu...