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Browse Prior Art Database

Associative Memory Cell

IP.com Disclosure Number: IPCOM000093445D
Original Publication Date: 1967-Sep-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Repchick, DP: AUTHOR

Abstract

This monolithic cell-provides large output voltages. R1, R2, R3, T5, and T6 form the basic bistable circuit for the cell. When T5 is turned on and T6 is turned off, a 1 is stored in the cell. When T6 is on and T5 is off, a 0 is stored in the cell.

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Associative Memory Cell

This monolithic cell-provides large output voltages. R1, R2, R3, T5, and T6 form the basic bistable circuit for the cell. When T5 is turned on and T6 is turned off, a 1 is stored in the cell. When T6 is on and T5 is off, a 0 is stored in the cell.

To interrogate the cell, either the 0 bit or 1 bit line is pulsed. If a 1 is stored in the cell when the 0 bit word line is pulsed, this pulse is not transmitted to transistor T7 and therefore there is no output to the sense amplifier. If a 0 is stored in the cell when 0 bit word line is pulsed, the pulse is transmitted through transistor T3 and transistor T6 to T7 and from there to the sense amplifier.

Likewise, if the 1 bit line is pulsed when a 0 is stored in the cell, no pulse is transmitted to T7. If a 1 is stored in the cell while the 1 bit line is pulsed, the pulse is transmitted through transistors T4 and T5 to T7. Therefore this cell is capable of performing an interrogate for match operation which is necessary for associative memories.

Sensing of the interrogate pulse is provided by T7 and transistor T8 which perform a current switching function. Transistors T9 and T10, in connection with the Vref, set the reference level to the base of T8 to distinguish between 0 and 1 interrogations at the base of T7.

T1 and T2 are clamping transistors, used to prevent T5 and T6 from saturating. If fast recovery times are not necessary, T1 and T2 can be eliminated.

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