Browse Prior Art Database

Encoder and Decoder for Error Correction and Detection

IP.com Disclosure Number: IPCOM000093487D
Original Publication Date: 1967-Oct-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Gorog, EP: AUTHOR

Abstract

The drawings show an implementation of cyclic codes as a departure from the usual systematic separable codes in which information and redundancy are ordinarily separable. Instead, here the encoded data is nonseparable as arrived at by use of a multiplying circuit in the encoder and a related division circuit in the decoder.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 57% of the total text.

Page 1 of 2

Encoder and Decoder for Error Correction and Detection

The drawings show an implementation of cyclic codes as a departure from the usual systematic separable codes in which information and redundancy are ordinarily separable. Instead, here the encoded data is nonseparable as arrived at by use of a multiplying circuit in the encoder and a related division circuit in the decoder.

In cyclic codes, multiplication of the information polynomial, by a generator polynomial directly, creates nonseparable codes. With the original information sequence gone from the altered encoded product, such codes have cryptographic aspects.

Implementation of the present cyclic code is shown in drawings A, B, and C, which are the encoder, decoder, and error corrector respectively, and is exemplified by a selected polynomial generating code of 1 + x/4/ + x/5/ + x/6/ + x/8/ for correction of a single-bit error in a message of 255 bots.

The eight-stage shift register multiplying encoder A has the required stages 20 and the selected intervening modulo-2 connections 21. This encoder dispenses with the usual two-position switch.

The error detection decoder or dividing register B involves register stages 22 and selectively placed modulo-2 connections 23. The code used in this example detects any single burst of errors less than or equal to eight, and there is only one nine error-burst pattern which is not detected. This nine error-burst consists of five erroneous bits, but through this implemen...