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# Digital Noise Filter Circuit

IP.com Disclosure Number: IPCOM000093569D
Original Publication Date: 1967-Nov-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 30K

IBM

## Related People

Waldecker, DE: AUTHOR [+2]

## Abstract

Any signal, which is less than the time T between the leading edges of the clock 1 and clock 2 pulses, is rejected and no output signal change is produced from polarity hold circuit 11. Thus, the circuit functions to filter noise of a duration less than T. The various conditions for circuit operation are shown in the following table: Initial Output Input Output Case State H Behavior Result 1. Down Up for 2 successive Goes up clocks 2. Up Down for 2 successive Goes down clocks 3. Up Down level noise in No change input but not at time of both clocks 4.

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Digital Noise Filter Circuit

Any signal, which is less than the time T between the leading edges of the clock 1 and clock 2 pulses, is rejected and no output signal change is produced from polarity hold circuit 11. Thus, the circuit functions to filter noise of a duration less than
T. The various conditions for circuit operation are shown in the following table: Initial Output Input Output

Case State H Behavior Result
1. Down Up for 2 successive Goes up

clocks
2. Up Down for 2 successive Goes down

clocks
3. Up Down level noise in No change

input but not at time

of both clocks
4. Down Up level noise in No change

input but not at time

of both clocks
5. Down Input stays down No change
6. Up Input stays up No change.

Considering, for example, the circuit operation for case 6, if the input signal at D is up when the leading edge of clock 1 pulse arrives at C, trigger 10 is set to produce an up signal at K. A down signal at K produces an up reset signal at And 13 of circuit 11.

If H is up at terminal 14, both signals to And 13 are up and the signal terminal stays up. Thus, an up input signal produces no polarity change at terminals 14 and 17. The same output occurs since the inputs to And 18 are also both up. If input signal is still up when clock 2 pulse occurs, an up signal occurs at terminal 14 from And 19 and And 18 as well as from And 13. If the input signal disappears before clock 2 pulse as in case 3, the output signals from And's 18 and 19 are down and an up si...