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Dual Mode Adder

IP.com Disclosure Number: IPCOM000093578D
Original Publication Date: 1967-Nov-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Goldschmidt, RE: AUTHOR

Abstract

The adder structure permits two modes of operation. In a first mode, three plural-bit operands can be simultaneously added together. In the second mode, two multiplicand multiples can be added to a previous partial product in the iterative operations of a binary multiplication problem. The basic adder structure consists of two carry-save adders CSA-A and CSA-B. The latter are comprised of full-adder stages, each stage of which receives three inputs and produces two outputs. One output represents the sum S of the inputs and the other represents the carry C of the inputs. Also included in the basic structure is Look-Ahead logic, which receives as inputs, the C and S functions of CSA-A which generate the propagate carry and generate carry functions. The Look-Ahead logic provides a Carry-In C-IN for each stage of the adder.

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Dual Mode Adder

The adder structure permits two modes of operation. In a first mode, three plural-bit operands can be simultaneously added together. In the second mode, two multiplicand multiples can be added to a previous partial product in the iterative operations of a binary multiplication problem. The basic adder structure consists of two carry-save adders CSA-A and CSA-B. The latter are comprised of full-adder stages, each stage of which receives three inputs and produces two outputs. One output represents the sum S of the inputs and the other represents the carry C of the inputs. Also included in the basic structure is Look-Ahead logic, which receives as inputs, the C and S functions of CSA-A which generate the propagate carry and generate carry functions. The Look-Ahead logic provides a Carry-In C-IN for each stage of the adder.

The first mode of operation requires the Look-Ahead apparatus to be enabled. Three plural-bit operands, Add 1, Add 2, and Add 3 are presented as inputs to CSA-A. The S function and C function of CSA-A are presented as inputs to CSA-B and to the Look-Ahead logic. The output C-IN of the Look-Ahead apparatus provides the third input to CSA-B. The final sum of the original three operands appears at the Result output of CSA-B.

In the second, or multiply mode of operation, two plural-bit multiples of a multiplicand, MPY 1 and MPY 2, are added to a previous partial product on each of successive iterations. In this mode of operation, the L...