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Internal Data Flow Control in Storage Hierarchies

IP.com Disclosure Number: IPCOM000093587D
Original Publication Date: 1967-Nov-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Belady, LA: AUTHOR [+2]

Abstract

This computer system utilizes a hierarchical memory organization comprising a high-speed core store backed up by either low-speed cores or a disk file or drum or all. In the system, transfers between storage devices are controlled by an expanded storage channel termed the gravity channel. This is loosely connected to the main frame. The connection is, in fact, only the sensing of changes in the storage-reference frequency-distribution updated by the actual processor or processors, and setting the allocation information to guide the processors' address linkage to the desired data, address mapping.

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Internal Data Flow Control in Storage Hierarchies

This computer system utilizes a hierarchical memory organization comprising a high-speed core store backed up by either low-speed cores or a disk file or drum or all. In the system, transfers between storage devices are controlled by an expanded storage channel termed the gravity channel. This is loosely connected to the main frame. The connection is, in fact, only the sensing of changes in the storage-reference frequency-distribution updated by the actual processor or processors, and setting the allocation information to guide the processors' address linkage to the desired data, address mapping.

This organization is an example of increasing parallelism. The appearance of channels, slave computers, or attached message buffering-switching satellite computers have all in common that the processor is capable of performing higher level tasks at high speed while simple internal data shuffling and moving can run at a slower speed.

Before transferring information between two different storage devices, it is necessary to know which block of information should move from fast to slow store, which block of information should move from slow to fast store in order to occupy the space previously held by a block having been pushed as previously, and when this 2-way move should be initiated. The above push-pull is termed the vertical flow in the storage system.

In this system, any processor is substantially freed not only from the task of initiating, moving, and controlling the vertical information flow but also from the decision making of what to move, in which direction and when.

So as to interfere with any processor as little as possible, the memory priority of the gravity channel should be low. The objective is function separation end prediction of storage access and movement patterns in all levels of the hierarchy. Previously, because of the storage devices' mechanical momentum, channel-initiated references have higher priority than any processor.

There is no need to do so in the case of a multilevel execution store hierarchy. Even with zero channel speed, the processor is running without interruption. In most cases, however, particularly with either interleaved memory banks or multiple buses or both, the channel flow can be quite fast. Thus, a gravity channel with lowest memory priority does not interfere with productive computational activity. Thus, advantage is taken of spare memory cycles to move data in the hierarchy ahead of time when the absence of data at the appropriate level could slow down computing activity.

In a multiprocessor, multiprogrammed or time-s...