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Noise Suppression for Memory with Ground Plane

IP.com Disclosure Number: IPCOM000093601D
Original Publication Date: 1967-Nov-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Sumilas, JW: AUTHOR

Abstract

The drawing shows bit-sense wires 2 and 3 of a conventional memory array. Wires 2 and 3 couple two groups of magnetic cores to a bit driver and to a differential sense amplifier. During a read operation, the bit driver supplies a half-select current to wires 2 and 3. As soon as the noise associated with the bit current ends, a word driver, not shown, is turned on to provide a second half-select current to switch a selected core. The waveform of the bit driver is shaped to minimize noise and to thus permit a faster memory cycle. This noise occurs because the memory array is positioned on a conductive ground plane that forms part of the circuit for the bit current.

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Noise Suppression for Memory with Ground Plane

The drawing shows bit-sense wires 2 and 3 of a conventional memory array. Wires 2 and 3 couple two groups of magnetic cores to a bit driver and to a differential sense amplifier.

During a read operation, the bit driver supplies a half-select current to wires 2 and 3. As soon as the noise associated with the bit current ends, a word driver, not shown, is turned on to provide a second half-select current to switch a selected core. The waveform of the bit driver is shaped to minimize noise and to thus permit a faster memory cycle. This noise occurs because the memory array is positioned on a conductive ground plane that forms part of the circuit for the bit current.

Most of the noise associated with the bit driver appears equally on the paired bit wires and is cancelled in the sense amplifier. However, there is an unbalanced noise voltage that is associated with differences in the information storage states of the cores on the two wires. This noise is proportional to the rate of change of the bit current and should exist only during the rise time of the bit current. However, the ground plane provides a high-conductance path in which these currents tend to persist.

In this memory, the bit current is made to slightly overshoot the half-select value indicated by dashed line 6 and to then decrease slowly to its half-select value. While the bit current is decreasing, the voltage induced in the ground plane is opposite in pol...