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Browse Prior Art Database

Low Buffer Power Memory Cell

IP.com Disclosure Number: IPCOM000093637D
Original Publication Date: 1967-Nov-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Agusta, B: AUTHOR [+2]

Abstract

The memory cell circuit decreases by an order of magnitude the standby buffer select power, permits substantially lower minimum values of transistor current gain, and allows the latch section of the cell to operate at a decreased level of saturation. The memory cell circuit includes NPN transistors T3 and T3' which perform the memory latching function in conjunction with resistors R1 and R2. NPN transistors T2 and T2' perform the current switching function during the read and write operations of the circuit. PNP transistors T1 and T1' perform the gain function when establishing the sense current level.

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Low Buffer Power Memory Cell

The memory cell circuit decreases by an order of magnitude the standby buffer select power, permits substantially lower minimum values of transistor current gain, and allows the latch section of the cell to operate at a decreased level of saturation. The memory cell circuit includes NPN transistors T3 and T3' which perform the memory latching function in conjunction with resistors R1 and R2. NPN transistors T2 and T2' perform the current switching function during the read and write operations of the circuit. PNP transistors T1 and T1' perform the gain function when establishing the sense current level.

The current IA is permitted to flow only to the selected cell of the matrix and its level is determined by the amount of sense signals required and the speed required in removing the base stored charge of the latch during the write cycle. A current, for example, of 1A = 0.4 milliamps, is a reasonable magnitude to draw off the stored base charge of T3 or T3' without causing appreciable write time delay in comparison to the RC time constant.

Due to the gain of T1 and T1', the current IA can be reduced by an order of magnitude than previously possible which reduces the select standby power by an order of magnitude. Further, T2 and T2' draw one order of magnitude less base current during the read cycle. This permits the latch to operate in a less saturated condition and possibly in an unbalanced active condition.

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