Browse Prior Art Database

Monolithic Module Layout

IP.com Disclosure Number: IPCOM000093638D
Original Publication Date: 1967-Nov-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Agusta, B: AUTHOR [+3]

Abstract

Drawings A and B show the electrical conductive land interconnection pattern used to electrically join two monolithic semiconductor chips together on a one half by one half inch alumina substrate. Drawing A shows the semiconductor chip locations 1 and 2. The semiconductor chips are mounted conductive pads down on suitable conductive lands to inter connect the semiconductor chips 1 and 2 to the top side of the substrate. Twelve interstitial pins 3 permit electrical contact to be made between the top and the bottom surfaces of the alumina substrate. Drawing B shows the land pattern on the bottom of the alumina substrate. The additional pins around the periphery of the alumina substrate are used to interconnect with the mounting card terminals.

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Monolithic Module Layout

Drawings A and B show the electrical conductive land interconnection pattern used to electrically join two monolithic semiconductor chips together on a one half by one half inch alumina substrate. Drawing A shows the semiconductor chip locations 1 and 2.

The semiconductor chips are mounted conductive pads down on suitable conductive lands to inter connect the semiconductor chips 1 and 2 to the top side of the substrate. Twelve interstitial pins 3 permit electrical contact to be made between the top and the bottom surfaces of the alumina substrate. Drawing B shows the land pattern on the bottom of the alumina substrate. The additional pins around the periphery of the alumina substrate are used to interconnect with the mounting card terminals.

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