Browse Prior Art Database

Recording Technique

IP.com Disclosure Number: IPCOM000093668D
Original Publication Date: 1966-Jan-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Barbeau, RA: AUTHOR

Abstract

The circuit minimizes the number of rewrites for a tape record in a system having the capability of ultimately reading the tape record and automatically correcting all read errors in at least one tape track. Such automatic read error correction is preferably of the type which can correct at least one track on the fly without requiring rereading of the block.

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Recording Technique

The circuit minimizes the number of rewrites for a tape record in a system having the capability of ultimately reading the tape record and automatically correcting all read errors in at least one tape track. Such automatic read error correction is preferably of the type which can correct at least one track on the fly without requiring rereading of the block.

Terminals TR1...TRN, respectively, receive the read-while-write outputs from the tracks on a magnetic tape being written. Circuit 10 detects, transfers or otherwise processes the tape signals during their transmission to a computer memory.

Envelope drop-out detectors D1...DN, respectively, sense each track for dropout. The tape tracks can be recorded with phase-encoded data in which pulsed signals are read for both 0 and 1 bits. A signal output from any D circuit indicates a dropout in its track and sets its respective latch of the group L1...LN.

Counter circuit 11 counts the number of tracks in error and provides an output indication at terminal 12 when errors occur in two or more tracks in a data block being written. The computer system receives the signal from terminal 12 and causes the data block to be rewritten only if more than one tape track is in error. The interblock gap prior to a rewritten block can be increased if desired to place the error-causing tape section in the gap, when more than one error in a block is signalled.

Counter 11 and all latches L1...LN are reset prior to wr...