Browse Prior Art Database

Increment Plus One Parity Generator

IP.com Disclosure Number: IPCOM000093682D
Original Publication Date: 1966-Jan-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Piankoff, V: AUTHOR

Abstract

Sequential reading of a memory requires incrementing the starting address by one repeatedly until the stop address is reached. Circuitry is shown for decoding the old address to generate the parity bit for the new, incremented, address.

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Increment Plus One Parity Generator

Sequential reading of a memory requires incrementing the starting address by one repeatedly until the stop address is reached. Circuitry is shown for decoding the old address to generate the parity bit for the new, incremented, address.

The addresses are in the form of binary numbers having odd parity. An arithmetic unit is used to add 1 to the old address to obtain the new, incremented, address. At the same time, the parity logic uses the old address to generate the parity bit for the new address. The new address, with its parity bit, is then checked by compare logic so that faulty operation of the arithmetic unit can be determined.

The old address is contained in two registers 20 and 21 comprising bits 3...15. The higher numbered bits are of lower order. Each register has its own parity bit which must be modified separately. Therefore, the old address is decoded by the logic to produce at output 22 the parity bit for the low-order portion of the new address, and at output 23 the parity bit for the high-order portion of the new address.

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