Browse Prior Art Database

CPU Priority with Shared Storage

IP.com Disclosure Number: IPCOM000093689D
Original Publication Date: 1966-Jan-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Bardsley, H: AUTHOR

Abstract

When two or more central processing units are sharing a storage unit, some form of priority scheme is necessary to decide which processor obtains the next storage reference. The priority circuits, when housed in the storage unit, introduce an added delay in the access time as far as the processor is concerned. The delay is incurred on every reference regardless of whether the other processor is making a request. If access time is critical to the processor this added delay may result in excessive performance degradation.

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CPU Priority with Shared Storage

When two or more central processing units are sharing a storage unit, some form of priority scheme is necessary to decide which processor obtains the next storage reference. The priority circuits, when housed in the storage unit, introduce an added delay in the access time as far as the processor is concerned. The delay is incurred on every reference regardless of whether the other processor is making a request. If access time is critical to the processor this added delay may result in excessive performance degradation.

In this arrangement, the priority circuits are removed from the storage unit and priority is established within the processors before the storage is referenced. The two processor internal clocks are running directly out of phase as shown. This can be accomplished by one CPU containing the master clock.

When CPU A selects the storage unit, it sends a CPU A Inhibit to B signal to the other processor preventing CPU B from selecting the storage during the same cycle. In effect, then, the inhibit signal blocks CPU B's select to storage, if any. CPU B cannot attempt another select until the next cycle. It does not do so because a Storage Busy indication is now present. Both processors may not select the storage unit until the busy indication disappears.

When the busy indication disappears, CPU B, now a half cycle ahead of CPU A, selects the non-busy storage and sends a CPU B Inhibit to A signal to processor A. With both...