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Memory with Bit Bypass

IP.com Disclosure Number: IPCOM000093699D
Original Publication Date: 1966-Jan-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Montren, JJ: AUTHOR

Abstract

The magnetic memory has planes 2...4 of magnetic cores 5. The single X wire shown is one of a large number of parallel wires. Each X wire runs through a row of cores in each plane. Similarly, a Y wire runs through a column of cores in each plane.

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Memory with Bit Bypass

The magnetic memory has planes 2...4 of magnetic cores 5. The single X wire shown is one of a large number of parallel wires. Each X wire runs through a row of cores in each plane. Similarly, a Y wire runs through a column of cores in each plane.

Selected X and Y wires are energized with currents of the appropriate level to operate on the one core in each plane that is threaded by both an X wire and a Y wire that are energized. The circuit is for controlling which planes are to be energized for writing a 1 and which are to be not energized for writing a 0.

One way to control the magnetization state of each of the cores in a word is to thread each core in a plane with a third inhibit wire. To write a 0 in a selected plane the inhibit wire is energized to carry current that opposes the combination of an X and Y wire and thus prevents writing a 1 in the plane.

This memory achieves an inhibiting effect in a memory having only vents writing a 1 in the plane.

This memory achieves an inhibiting effect in a memory having only two wires for each memory element. For each plane there is a bypass conductor 6...8 that parallels the Y conductors that thread the cores of the plane. A matrix of switches is provided between each plane for directing the Y current to either the bypass conductor or to the conductor that threads the cores.

In the drawing, there is shown a pair of switches 9 and 12, 10 and 13, 11 and 14, for each plane. For example, closing swit...