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Nondestructive Readout Memory Cell using MOS Transistors

IP.com Disclosure Number: IPCOM000093721D
Original Publication Date: 1966-Jan-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Pleshko, P: AUTHOR

Abstract

Metal-oxide-semiconductor MOS transistors have electrical properties which make them especially suitable for use in nondestructive readout NDRO memory cells. The drawing shows a single NDRO memory cell using MOS transistors. This arrangement is adapted particularly for use in a word oriented memory. The expression MOS transistor as used here is equivalent, for practical purposes, with insulated-gate-field-effect transistor IGFET.

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Nondestructive Readout Memory Cell using MOS Transistors

Metal-oxide-semiconductor MOS transistors have electrical properties which make them especially suitable for use in nondestructive readout NDRO memory cells. The drawing shows a single NDRO memory cell using MOS transistors. This arrangement is adapted particularly for use in a word oriented memory. The expression MOS transistor as used here is equivalent, for practical purposes, with insulated-gate-field-effect transistor IGFET.

Each memory cell comprises six transistors 1...6. Transistors 1 and 2, with the gate electrodes of one cross coupled to the drain electrode of the other, constitute a storage flip-flop. Digit 1 is stored when transistor MOS 1 is conducting but transistor MOS 2 is not conducting. Digit 0 is stored when MOS 2 is conducting but MOS 1 is not conducting. The flip-flop is switched by causing current to flow from a selected input circuit into the drain node of the nonconducting MOS. For instance, assume that the flip-flop initially is storing a 0,
i.e., MOS 1 is not conducting. Assume further that a 1 bit pulse is applied to the gate of MOS 3 simultaneously with the application of a word select pulse to the gate of MOS 5. MOS's 3 and 5 now function as a two-element And causing current to flow through drain resistor R1. The voltage change across R1 is communicated to the gate MOS 2, causing the latter to cease conducting. This, in turn, causes MOS 1 to start conducting and the nip-flop now is in its 2 state. A converse action occurs when the flip-flop is switched from 1 to 0. In this instance, word select MOS 5 and 0 bit input MOS 4 act as a two-element And for establishing current flow through drain resistor R2. This results in occurs when the flip-flop is switched from 1 to 0. In this instance, word select MOS 5 and 0 bit input...