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Ultra High Speed Switching Circuit

IP.com Disclosure Number: IPCOM000093725D
Original Publication Date: 1966-Jan-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Jen, TS: AUTHOR

Abstract

This is a high speed logic switching circuit. It provides a temporary push-pull energization to a current switch output circuit for increasing its speed of operation.

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Ultra High Speed Switching Circuit

This is a high speed logic switching circuit. It provides a temporary push-pull energization to a current switch output circuit for increasing its speed of operation.

Transistor pairs T1 and T2 and T3 and T4 are respectively connected in the current switch configuration. The emitters of T1 and T2 and T3 and T4 are connected via resistors 6 and 8 to negative supplies. The output stage of the switching circuit is also a current switch. This includes transistors T10 and T12 whose emitters are also connected through a common resistor 14 to the negative supply.

T1 is rendered conductive when the input voltage Va is applied via conductor 16 to its base and is at the up logical level. As a result, the common emitter potential of T1 and T2 rises. Such rise is to a level sufficiently positive with respect to the base potential of T2 to prevent its conduction, i.e., normal current switch action. The collector potential of T2 is thus at a relatively high level and is transmitted via conductor 18 to the base of T4. The latter is rendered conductive and, in turn, renders T3 nonconductive via the potential rise across common emitter resistance 8. The collectors of T1 and T3 are both connected through conductor 20 to the base of T10. The level of voltage Vb at the base of T10 is, under these conditions, determined by the current flowing through T1, T3 being nonconductive. This level is portion 50 of waveform Vb.

As input voltage Va transiently falls to the low logic level, as in portion 52 of waveform Va, T1 ceases conduction before T3 begins to conduct. This occurs due to the fact that there is a two stage dela...