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Inhibit Circuit

IP.com Disclosure Number: IPCOM000093729D
Original Publication Date: 1966-Jan-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Jen, TS: AUTHOR

Abstract

This logical inhibit circuit through the use of current switching techniques employs one logical input to inhibit the operation of circuitry receiving additional logical inputs.

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Inhibit Circuit

This logical inhibit circuit through the use of current switching techniques employs one logical input to inhibit the operation of circuitry receiving additional logical inputs.

Transistors T1 and T2 are connected in the current switch configuration. The base reference of T2 is taken across the split collector resistor of T1 via conductor 8. Transistors T3 and T4 are also connected in the current switch configuration. T3 further controls the operation of current switch transistors T5, T6, and T7. If inhibit input A is applied to the base of T1 and is at the up logical level. T1 is rendered conductive, causing its collector potential to fall. This decrease in collector potential results in a like decrease on conductor 8 which renders T2 nonconductive. The reason for deriving the potential at the base of T2 from the split collector resistor of T1 is later discussed. With T2 nonconductive, its high collector potential, as transmitted through conductor 10, results in the conduction of T4.

This action, in combination with the relatively low collector potential of T1 as reflected through conductor 12 to the base terminal of T3 renders T3 nonconductive. With T3 nonconductive no emitter supply is applied to T5, T6, or T7 and they are rendered incapable of operation. Thus logical inputs B and C are prevented from affecting output terminals 14 and 16

When the A inhibit input goes to the down logical level, T1 is rendered nonconductive. In response to the rise in collector potential of T1, as ref...