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Simultaneous Surface Potential Control and Oxide Stabilization of Silicon IGFET

IP.com Disclosure Number: IPCOM000093732D
Original Publication Date: 1966-Jan-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Fang, FF: AUTHOR

Abstract

This technique is for controlling the surface potential and, also, for stabilizing the silicon dioxide insulating layer in an insulated-gate field effect transistor simultaneously.

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Simultaneous Surface Potential Control and Oxide Stabilization of Silicon IGFET

This technique is for controlling the surface potential and, also, for stabilizing the silicon dioxide insulating layer in an insulated-gate field effect transistor simultaneously.

As shown, the field effect transistor comprises source and drain electrodes 1 and 3 of first conductivity type diffused into semiconductor wafer 5 of opposite conductivity type. The narrow surface portion of wafer 5 intermediate source and drain electrodes 1 and 3 defines conduction channel 7. Silicon dioxide layer 9 is formed over the surface of wafer 5. Gate electrode 11 is formed over layer 9 and registered in electric field-applying relationship with conduction channel 7. Electrical access to source and drain electrodes 1 and 3 is provided by opening windows 13 in layer 9.

Gallium (Ga) can be diffused through layer 9 to control surface potential along conduction channel 7 and hence tailor the threshold voltage of the insulated-gate field effect transistor. Also phosphorus (P) or arsenic (As) diffused into layer 9 has the effect of stabilizing such layer. Accordingly, under appropriate conditions, both effects are achieved simultaneously by diffusing a compound of such materials e.g. gallium phosphide (Ga) or gallium arsenide (GaAs) into layer 9 over conduction channel 7 prior to the metallization of gate electrode 11. At 500 degrees C the equilibrium pressures of gallium and phosphorus are approximately...