Browse Prior Art Database

Testing of Integrated Circuits

IP.com Disclosure Number: IPCOM000093736D
Original Publication Date: 1966-Jan-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Donath, WE: AUTHOR

Abstract

The technique is for testing an integrated circuit arrangement. Such testing avoids physical contact of mechanical probes with a supporting substrate.

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Testing of Integrated Circuits

The technique is for testing an integrated circuit arrangement. Such testing avoids physical contact of mechanical probes with a supporting substrate.

An integrated circuit arrangement as represented by NPN transistor T is formed in silicon substrate 1. Emitter, base, and collector regions of T are connected along conductors 3, 5, and 7. Such conductors extend over silicon dioxide insulating layer 9 to operating sources not shown. Thin layer 11 of photoconductive material, e.g., lead sulphide (PbS), lead selenide (PbSe), etc., and layer 13 of an electrolytic gel material or tin oxide (SnO), are formed over substrate 1. The latter is connected to a variable voltage source. Transistor T can be biased either for conduction or nonconduction.

When T is biased for conduction, a narrow beam of light 15 is directed onto portions of layer 11 to electrically connect conductor 3 and layer 13. Layer 13 is maintained at a voltage sufficiently positive to turn off T. When T is biased for nonconduction, light beam 15 can be directed onto portions of layer 11 to electrically connect conductor 5 and layer 13. Layer 13 is maintained at a voltage sufficiently positive to turn on T. Proper operation of T is ascertained by sensing variations in temperature at the device area by I-R pyrometer 17 focused on substrate 1.

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