Browse Prior Art Database

Serialization and Deserialization System

IP.com Disclosure Number: IPCOM000093764D
Original Publication Date: 1966-Feb-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

de Backer, P: AUTHOR [+3]

Abstract

This system is capable of performing both serialization and deserialization at a processing level of stored bits in a word memory.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 96% of the total text.

Page 1 of 2

Serialization and Deserialization System

This system is capable of performing both serialization and deserialization at a processing level of stored bits in a word memory.

The system uses existing portions of a standard computer. The additional circuits required to perform the functions are few. The needed instructions are mainly standard ones, i.e., shift-left or shift-right, single or double.

In the core memory schematically represented, n words W1 to Wn have been, sequentially entered. Each word, such as Wi, is composed of p bits such as A1i, A2i...Aki...Api. Serialization process consists in simultaneously reading out all the bits belonging to a given rank k of these words for example Ak1, Ak2...Aki...Akn.

For this purpose, bits of rank k from words W1...Wn are loaded into register Q as follows. The first word W1 is fed to register R through the memory read- write register. Register R contents are shifted k-1 ranks to the right so that the k/th/ bit of word W1,for example, Ak1, comes to the right extremity of register R. Then registers R and Q are both shifted to the right double shift by one rank and the operand address is incremented by one. The same operation goes on with the next word and so on until the last word Wn is reached. When all words are processed register Q then contains all the bits of rank k from words W1... Wn.

Deserialization process i.e. store bits from register Q into ranks k of the core memory, can be performed by the same circuitry.

1

P...