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# Modulo Two Logic Circuits

IP.com Disclosure Number: IPCOM000093765D
Original Publication Date: 1966-Feb-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 56K

IBM

## Related People

Marcus, MP: AUTHOR

## Abstract

Any desired Boolean expression of at least three variables and at least two terms having a plurality of such variables can be implemented by a logic circuit comprising a single modulo-two logic block and a plurality of basic logic blocks such as And's, Or's, etc., each of identical configuration. All inputs to such logic circuit can occur in a predetermined one of their two available complementary forms. That is, complemented inputs are not necessary.

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Modulo Two Logic Circuits

Any desired Boolean expression of at least three variables and at least two terms having a plurality of such variables can be implemented by a logic circuit comprising a single modulo-two logic block and a plurality of basic logic blocks such as And's, Or's, etc., each of identical configuration. All inputs to such logic circuit can occur in a predetermined one of their two available complementary forms. That is, complemented inputs are not necessary.

A sum modulo-two block performs a + function which equals 1 only when an odd number of the inputs equals 1. A dot modulo-two block performs a . function which equals 1 only when an even number, including none of the inputs equals 0. In drawings 1A...1D are examples of modulo-two circuit implementations using positive logic. Blocks in column 1A give an output of 1 only when an odd number of the inputs is 1. Those in 1B give an output of 1 only when an even number of the inputs is 1. Those in 1C give an output of 1 only when an even number of the inputs is 0. Those in 1D give an output of 1 only when an odd number of the inputs is 0. By way of example sum mod-two blocks can be combined with one or more And's to perform various functions such as those indicated in drawings 2A...2D.

These sum mod-two blocks can be used in a variety of combinational and sequential logic circuitry such as the full adder and latch circuits in drawings 3A and 3B, respectively.

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