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Increasing Main Memory Speeds Through the Use of Temporary Storage

IP.com Disclosure Number: IPCOM000093787D
Original Publication Date: 1966-Feb-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Sakalay, FE: AUTHOR

Abstract

Standard core storage 10 with associated address register 11 has two modes of operation. One mode is called a Store and the other mode is termed a Fetch. The storage cycle Fetch or Store is made up of two parts, the Read portion and the Write portion. During a Fetch the Read portion of the cycle clears the addressed location and the Write portion regenerates the original data back in memory. During a Store the Read portion also clears the addressed location and the Write portion sets new data into storage.

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Increasing Main Memory Speeds Through the Use of Temporary Storage

Standard core storage 10 with associated address register 11 has two modes of operation. One mode is called a Store and the other mode is termed a Fetch. The storage cycle Fetch or Store is made up of two parts, the Read portion and the Write portion. During a Fetch the Read portion of the cycle clears the addressed location and the Write portion regenerates the original data back in memory. During a Store the Read portion also clears the addressed location and the Write portion sets new data into storage.

Consider a storage in which the Read and Write portions of the cycle are completely independent of each other. This means that the storage can execute cycles in which the Read is not followed by a Write and in which the Write is not preceded by a Read. Then if this storage executes successive Reads of data onto an output bus 12, no regeneration, the repetition rate or cycle time is doubled. Since some of the data being read must be restored to storage for future use, this data on bus 12 and its address on line 13 are filed temporarily in small fast temporary store 14. Whenever core storage becomes idle data from store 14 is returned to main storage on bus 15 through Or 16. The address, previously stored with the data word, is also read out of store 14 to register 11. Because the locations in core storage being written into are cleared during a previous Read, consecutive Writes can occur at the s...