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Multiple Shifter with Overflow Detection

IP.com Disclosure Number: IPCOM000093820D
Original Publication Date: 1966-Mar-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 3 page(s) / 50K

Publishing Venue

IBM

Related People

Prentice, PN: AUTHOR

Abstract

This parallel word data shifter shifts a double word of sixty-four bits to either the right or left by up to thirty-two bit positions. The word to be shifted can be in either true or complement form. For a right-shift, the word is automatically filled in, in the vacated spaces at the left, with bits which are the same as the sign bit. For a left-shift, the bits shifted off the left end of the shifted word are checked to detect loss of a significant digit.

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Multiple Shifter with Overflow Detection

This parallel word data shifter shifts a double word of sixty-four bits to either the right or left by up to thirty-two bit positions. The word to be shifted can be in either true or complement form. For a right-shift, the word is automatically filled in, in the vacated spaces at the left, with bits which are the same as the sign bit. For a left-shift, the bits shifted off the left end of the shifted word are checked to detect loss of a significant digit.

A data word to be shifted is stored in input register 1. The word has its sign bit, 0 for a positive number and 1 for a negative number, in the leftmost bit position. The extent to which the word is to be shifted is here illustrated as a left- shift of thirteen. A shift can be any number of bit positions up to thirty-two either to the right or to the left, indicated by a combinational energization of lines 2. The latter operate shift control decoder 3.

Four shifters 4...7 are controlled by outputs of decoder 3 to selectively connect each shifter input line to one shifter output line. The latter may or may not be displaced in denominational significance, as determined by the applicable output of decoder 3. Shifter 4 can be controlled by decoder 3 to shift input signals, received on lines connecting it to register 1, to output lines representing a shift of 0, left L1, or left L2 denominations. Outputs of shifter 4 are inputs to shifter 5 which can be set to cause a shift of 0 or a left shift of L2, L4, or L6 denominations.

Shifter 6 can similarly be set for a 0 shift or a left shift of L8 or L16 bit spaces. Shifter 7 is settable for a 0 shift, a left shift of L24 spaces, or a right shift of R16 spaces. Thus, any shift extent from forty-eight left to sixteen right can be selected for the word in register 1 by selective energization of decoder 3.

The left end of shifter 4 is extended two bit positions to the left to provide outputs for an additional two bits. For any selected shift, these two outputs receive those bit signals of orders 1 and 2 of register 1 which are shifted from the rightmost sixty-three bits of shifter 4. The sign bit in register 1 position 0, in all cases, passes through each shifter 4...7, without a shift irrespective of the setting of decoder 3, and is also fanned out into those outputs of the two-bit left extension of shifter 4 which do not receive an input from register 1.

The left ends of shifters 5...7 are extended to the left to provide eight, twenty- four, and thirty-two additional bit positions respectively. For shifter 5, an...