Browse Prior Art Database

Multilayer Electronic Packages

IP.com Disclosure Number: IPCOM000093824D
Original Publication Date: 1966-Mar-01
Included in the Prior Art Database: 2005-Mar-06
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Related People

Beverly, NE: AUTHOR [+2]

Abstract

In electronic package 9, electrical connections are made between a plurality of chips 10 and printed circuit board 11 by a plurality of wiring layers 12. The latter are held together under pressure to allow disassembly of package 9 and removal or replacement of any layer. Chips 10 are mounted on chip holder 13 that abuts or is bonded to heat sink 14 in the form of a hollow copper block through which a coolant fluid is circulated.

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Multilayer Electronic Packages

In electronic package 9, electrical connections are made between a plurality of chips 10 and printed circuit board 11 by a plurality of wiring layers 12. The latter are held together under pressure to allow disassembly of package 9 and removal or replacement of any layer. Chips 10 are mounted on chip holder 13 that abuts or is bonded to heat sink 14 in the form of a hollow copper block through which a coolant fluid is circulated.

Chips 10 in excess of the number required to produce a satisfactory yield are mounted on holder 13. Chips 10 are tested to determine which ones are good. The first layer or layers 12 immediately adjacent chips 10 are designed to connect the good chips to a layer 12 having a standard interface. Layer 12 with the standard interface and the remaining layers act as a space transformer for connecting the connections from the good chips to board 11 to provide the desired logic for the package.

Each chip 10 is mounted in a socket 15 milled into chip holder 13. Chips 10 are soldered to copper block 16 into which socket 15 extends. The various terminals on chips 10 are connected by fine gold wires 17 to the appropriate one of a plurality of insulated conductive layers 18...20. Recesses 21 are milled around the edge of socket 15 to expose areas, on the under layers, for connection to appropriate wires 17. Inner layers 18 and 19, and block 16, provide the various biasing voltages for chips 10. Outer layer 20, comprising a plurality of separated conductive lands, provides for feeding signals to the chips.

Each layer 12 comprises plastic sheet 22 having the desired conductive l...